TC 91

Electronics assembly technology

 

P-Members vote

P-Members

Voting
P-Members

In favour
In favour %
Criteria
Result
6 6 100 >=66.7% APPROVED

All Votes

Total

Votes Cast
Total

Against
Against %
Criteria
Result
9 0 0 <=25% APPROVED

 Illustration: Voting

Voting Result

APPROVED

Document 91/1713/FDIS

 

Project : IEC 62530-2 ED1

IEC 62530-2 ED1: SystemVerilog – Part 2: Universal Verification Methodology Language Reference Manual (IEEE Std 1800.2-2017)

 

Reference Circulation date Closing date Downloads
91/1713/FDIS 2021-03-05 2021-04-16

Compilation of Comments
CC file    
 
export to xls file

Result of Voting

Country
Status
Received
Vote
Comments
Austria O 2021-04-15 A -
Belgium O 2021-04-16 A -
Brazil O -
Bulgaria O -
China P 2021-04-06 Y -
Czech Republic O -
Democratic People's Republic of Korea - 2021-04-11 Y -
Denmark O -
Finland P 2021-03-11 A -
France O 2021-04-16 A -
Germany P 2021-03-30 Y -
Greece - 2021-04-16 A -
Hungary O -
India P 2021-04-01 A -
Israel O -
Italy P 2021-04-15 A -
Japan P 2021-04-13 Y -
Korea, Republic of P 2021-04-16 Y -
Netherlands P 2021-04-15 A -
Norway O -
Poland O -
Portugal O 2021-04-16 A -
Qatar - 2021-04-14 Y -
Romania O -
Russian Federation P 2021-04-16 Y -
Serbia O -
Slovenia O -
Spain O -
Sweden O -
Switzerland O -
Turkey O -
Ukraine O -
United Arab Emirates - 2021-04-13 Y -
United Kingdom P 2021-04-06 Y -
United States of America P 2021-04-16 A -

NOTES:



  1. Vote: Does the National Committee agree to publish the FDIS as an International Standard?
    Y = In favour; N = Against; A = Abstention.

  2. Abstentions are not taken into account when totalizing the votes.

  3. P-members not voting: (0).


*Comments not included in the compiled table, available as a separate file, because they were not submitted using the template Form-Comments.