International Standards and Conformity Assessment for all electrical, electronic and related technologies

TC 91

Electronics assembly technology

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

TC 91WG 2 WPUB  

History

Stage
Document
Downloads
Decision Date
Target Date
CFDIS
93/213/FDIS
2005-01-21 
APUB
93/218/RVD PDF file 67 kB
2005-03-282005-04
BPUB
2005-03-29 
DECFDIS
2005-04-04 
DECPUB
2005-04-04 
RFDIS
2005-04-27 
PPUB
2005-06-272005-05
WPUB
93/292/RR PDF file 19 kB
2010-08-04 
  

Abstract

Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Project

IEC 62142:2005 ED1

Verilog (R) register transfer level synthesis

 

 

Associated Documents:

93/271/MCR

PDF file 61 kB