International Standards and Conformity Assessment for all electrical, electronic and related technologies

SC 47D

Semiconductor devices packaging

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

SC 47DWG 2 Hirofumi NAKAJIMAPPUB2011-022021

History

Stage
Document
Downloads
Decision Date
Target Date
PNW
47D/653/NP PDF file 761 kB
2006-04-14 
ANW
47D/666/RVN PDF file 151 kB
2006-08-252006-08
1CD
47D/690/CD PDF file 394 kB
2007-06-152007-04
CDM
47D/705/CC PDF file 115 kB
2007-10-122007-10
A2CD
47D/705A/CC Word file 91 kB
PDF file 81 kB
2008-08-222007-12
2CD
47D/724/CD PDF file 338 kB
2008-08-222008-08
ACDV
47D/735A/CC PDF file 57 kB
2009-01-232008-12
CCDV
47D/750/CDV PDF file 482 kB
PDF file 459 kB
2009-08-282009-10
AFDIS
47D/766/RVC Word file 159 kB
PDF file 269 kB
2010-02-262010-04
DECFDIS
2010-08-302010-05
RFDIS
2010-08-312010-09
CFDIS
47D/785/FDIS

2010-11-052010-11
APUB
47D/793/RVD PDF file 210 kB
2011-01-122011-01
BPUB
2011-01-132011-01
PPUB
2011-01-272011-02
  

Project

IEC 60191-6-17:2011 ED1

Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

 

 

Associated Documents:

47D/901A/RM

PDF file 145 kB
SMB/3500/DL

PDF file 166 kB
SMB/3445B/INF

PDF file 102 kB