International Standards and Conformity Assessment for all electrical, electronic and related technologies

ISO/IEC JTC 1/SC 25

Interconnection of information technology equipment

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

ISO/IEC JTC 1/SC 25 PPUB  

History

Stage
Document
Downloads
Decision Date
Target Date
PPUB
1991-12-17 
  

Abstract

Describes a high-performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on IEC 60297. Note: -1.This bus is similar to the VME bus. 2.For the price of this publication, please consult the ISO/IEC price-code list.

Project

IEC 60821:1991 ED2

VMEbus - Microprocessor system bus for 1 byte to 4 byte data