International Standards and Conformity Assessment for all electrical, electronic and related technologies

TC 91

Electronics assembly technology

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

TC 91WG 2 WPUB  

History

Stage
Document
Downloads
Decision Date
Target Date
CFDIS
93/212/FDIS
2005-01-21 
APUB
93/217/RVD PDF file 67 kB
2005-03-282005-04
BPUB
93/217/RVD PDF file 67 kB
2005-03-29 
DECPUB
2005-04-04 
DECFDIS
2005-04-04 
RFDIS
2005-04-20 
PPUB
2005-07-19 
WPUB
93/291/RR PDF file 19 kB
2010-08-04 
  

Abstract

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Project

IEC 62050:2005 ED1

VHDL Register Transfer Level (RTL) synthesis