International Standards and Conformity Assessment for all electrical, electronic and related technologies

TC 91

Electronics assembly technology

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

TC 91WG 13 PPUB 2023

History

Stage
Document
Downloads
Decision Date
Target Date
CFDIS
93/303/FDIS
2010-11-12 
APUB
93/305/RVD PDF file 25 kB
2011-01-172011-02
DECPUB
2011-01-17 
BPUB
2011-01-18 
RPUB
2011-04-01 
PPUB
2011-05-192011-03
  

Abstract

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

Project

IEC 62530:2011 ED2

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

 

 

Associated Documents:

23E/994/RM

PDF file 3201 kB