International Standards and Conformity Assessment for all electrical, electronic and related technologies

TC 91

Electronics assembly technology

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

TC 91WG 2 K TabuchiWPUB2002-05 

History

Stage
Document
Downloads
Decision Date
Target Date
PNW
93(JP)/1/NP  
1994-01-01 
ANW
93(SEC.)/15/RVN  
1994-05-15 
1CD
93/110/CD PDF file 302 kB
1999-08-131998-10
ACDV
93/122/CC PDF file 15 kB
2000-09-011999-12
CCDV
93/139/CDV PDF file 311 kB
2001-05-112000-11
AFDIS
93/147/RVC Word file 90 kB
PDF file 111 kB
2001-12-212002-01
RFDIS
2002-01-042002-01
DECFDIS
2002-01-042002-05
CFDIS
93/151/FDIS
2002-02-082002-04
APUB
93/153/RVD PDF file 21 kB
2002-04-232002-06
BPUB
2002-04-242002-07
PPUB
2002-05-172002-06
WPUB
93/311/RR PDF file 21 kB
2011-06-01 
  

Abstract

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Project

IEC 61523-2:2002 ED1

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

 

 

Associated Documents:

93/89/RM

PDF file 59 kB
93/79/RM

PDF file 69 kB
93/306/RM

PDF file 48 kB
93/266/MCR

PDF file 61 kB
CA/1869/MTG

PDF file 127 kB