International
Electrotechnical
Commission
International Standards and Conformity Assessment
for all electrical, electronic and related technologies
TC 91 |
Electronics assembly technology |
Detail
Committee | Working Groups | Project Leader | Current Status |
Frcst Pub Date | Stability Date |
|---|---|---|---|---|---|
| TC 91 | WG 2 | WPUB |
History
Stage | Document | Downloads | Decision Date | Target Date | ||
|---|---|---|---|---|---|---|
| CFDIS |
| 2005-01-21 | ||||
| APUB |
| 2005-03-28 | 2005-04 | |||
| BPUB | 2005-03-29 | |||||
| DECFDIS | 2005-04-04 | |||||
| DECPUB | 2005-04-04 | |||||
| RFDIS | 2005-04-27 | |||||
| PPUB | 2005-06-27 | 2005-05 | ||||
| WPUB |
| 2010-08-04 | ||||
Project
IEC 62142:2005 ED1
Verilog (R) register transfer level synthesis
Associated Documents:
93/271/MCR
61 kB