International Standards and Conformity Assessment for all electrical, electronic and related technologies

ISO/IEC JTC 1/SC 25

Interconnection of information technology equipment

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

ISO/IEC JTC 1/SC 25 PPUB  

History

Stage
Document
Downloads
Decision Date
Target Date
BPUB
1998-08-24 
RFDIS
1998-10-12 
DECFDIS
1999-09-16 
RPUB
1999-11-09 
PPUB
2000-07-311998-11
  

Abstract

The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).

Project

ISO/IEC 13961:2000 ED1

Information technology - Scalable Coherent Interface (SCI)