International Standards and Conformity Assessment for all electrical, electronic and related technologies

ISO/IEC JTC 1/SC 25

Interconnection of information technology equipment

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

ISO/IEC JTC 1/SC 25 PPUB 2023

History

Stage
Document
Downloads
Decision Date
Target Date
DECPUB
2003-05-13 
RFDIS
2003-05-152003-05
RPUB
2003-06-05 
BPUB
2004-11-052003-07
PPUB
2004-12-152003-08
  

Abstract

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) website.

Project

ISO/IEC 18372:2004 ED1

Information technology - RapidIO TM interconnect specification