SC 47D |
Semiconductor devices packaging |
SC 47D Work programme (6)
Project Reference |
Document Reference |
Init. Date |
Current Stage |
Next Stage |
Working Group |
Project Leader |
Fcst. Publ. Date |
|---|---|---|---|---|---|---|---|
|
PWI TR 47D-3 ED1
Future IEC TR 60191-7-5 Ed.1: 3D semiconductor package model for precise thermal analysis (JTAM)
|
PWI
2020-07 |
2020-07 |
Yutaka Kumano | ||||
|
PWI TR 47D-5 ED1
Future IEC TR 60191-7-2 Ed.1: Thermal conductivity measurement method and samples for electronic components
|
PWI
2020-07 |
2020-11 |
Yutaka Kumano | ||||
|
PWI TR 47D-6 ED1
Future IEC TR 60191-7-4 Ed.1: Printed circuit board specifications to evaluate thermal characteristics of fine pitch semiconductor packages
|
PWI
2020-07 |
2020-11 |
Yutaka Kumano | ||||
|
PNW 47D-926 ED1
Future 63xxx-2 Ed.1: Thermal standardization on semiconductor packaging – Part 2: 3D thermal simulation models of semiconductor packages for steady-state analysis
|
47D/926/NP |
PRVN
2021-03 |
2021-04 |
WG 2 | Yutaka Kumano | 2023-12 | |
|
PNW 47D-927 ED1
Future 63xxx-3 Ed.1: Thermal standardization on semiconductor packaging – Part 3: Thermal circuit simulation models of semiconductor packages for transient analysis
|
47D/927/NP |
PRVN
2021-04 |
2021-05 |
WG 2 | Yutaka Kumano | 2023-12 | |
|
IEC TR 63378-1 ED1
Thermal standardization on semiconductor packages – Part 1: Thermal resistance and thermal parameter of BGA, QFP type semiconductor packages
|
47D/928/DTR | 2021-02 |
CDTR
2021-02 |
PRVDTR
2021-04 |
WG 2 | Yutaka Kumano | 2021-12 |
656 kB