International Standards and Conformity Assessment for all electrical, electronic and related technologies

SC 47D

Semiconductor devices packaging

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub
Date

Stability

Date

SC 47D02Hirofumi NAKAJIMAPPUB2011-022016

History

Stage
Document
Downloads
Decision Date
Target Date
PNW
47D/653/NP pdf file 760 kB
2006-04-14 
ANW
47D/666/RVN pdf file 150 kB
2006-08-252006-08-31
1CD
47D/690/CD pdf file 393 kB
2007-06-152007-04-30
CDM
47D/705/CC pdf file 114 kB
47D/705A/CC doc file 91 kB
pdf file 80 kB
2007-10-122007-10-31
A2CD
47D/705/CC pdf file 114 kB
47D/705A/CC doc file 91 kB
pdf file 80 kB
2008-08-222007-12-31
2CD
47D/724/CD pdf file 338 kB
2008-08-222008-08-31
ACDV
47D/735/CC pdf file 9 kB
47D/735A/CC pdf file 56 kB
2009-01-232008-12-31
CCDV
47D/750/CDV pdf file 481 kB
pdf file 459 kB
47D/750F/CDV pdf file 459 kB
2009-08-282009-10-31
ADIS
47D/766/RVC doc file 159 kB
pdf file 269 kB
2010-02-262010-04-30
DEC
2010-08-302010-05-31
RDIS
2010-08-312010-09-15
CDIS
47D/785/FDIS

2010-11-052010-11-30
APUB
47D/793/RVD pdf file 209 kB
2011-01-122011-01-15
BPUB
2011-01-132011-01-31
PPUB
2011-01-272011-02-28

Project

IEC 60191-6-17 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

 

Remark:

- Targets extended for 1CD: 2007-04 - SMB/3500/DL - cc: TC 40

 

Associated Documents:

SMB/3445B/INF

SMB/3500/DL