International
Electrotechnical
Commission
International Standards and Conformity Assessment
for all electrical, electronic and related technologies
SC 47D |
Semiconductor devices packaging |
Detail
Committee | Working Groups | Project Leader | Current Status | Frcst Pub Date | Stability Date |
|---|---|---|---|---|---|
| SC 47D | 02 | Masashi OTSUKA | PPUB | 2010-09 | 2016 |
History
Stage | Document | Downloads | Decision Date | Target Date | ||||
|---|---|---|---|---|---|---|---|---|
| PNW |
| 2008-05-09 | ||||||
| ANW |
| 2008-09-19 | 2008-09-30 | |||||
| 1CD |
| 2008-11-28 | 2009-09-30 | |||||
| ACDV |
| 2009-03-20 | 2009-04-30 | |||||
| CCDV |
| 2009-05-08 | 2009-04-30 | |||||
| ADIS |
| 2010-01-08 | 2010-01-15 | |||||
| DEC | 2010-04-29 | 2010-01-31 | ||||||
| RDIS | 2010-05-04 | 2010-05-15 | ||||||
| CDIS |
| 2010-06-11 | 2010-07-31 | |||||
| APUB |
| 2010-08-17 | 2010-08-15 | |||||
| BPUB | 2010-08-18 | 2010-08-31 | ||||||
| PPUB | 2010-08-30 | 2010-09-30 | ||||||
331 kBProject
IEC 60191-6-20 Ed. 1.0
Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)
Remark:
- Targets CDV: 2010-09 FDIS: 2011-06