International Standards and Conformity Assessment for all electrical, electronic and related technologies

SC 47D

Semiconductor devices packaging

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

SC 47D02Masashi OSTUKADEL2007-12 

History

Stage
Document
Downloads
Decision Date
Target Date
PNW
47D/574/NP pdf file 945 kB
2004-01-30 
ANW
47D/593/RVN pdf file 148 kB
2004-09-032004-06-15
PWI
2006-09-292005-12-31
PNW
47D/670/NP pdf file 382 kB
2006-11-03 
DEL
47D/695/RVN pdf file 120 kB
2007-06-292007-03-31

Project

IEC 60191-6-14 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-14: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)

 

Remark:

- PR put to PWI acc to decision at Berlin, 2006-09-29 -then restart with NP-CD - US No 2/03-029 - Extension of targets approved by SMB/3099/R Cape Town 05-10-17

 

Associated Documents:

SMB/3130/DL

SMB/3298A/INF

47D/671/CD