International Standards and Conformity Assessment for all electrical, electronic and related technologies

SC 47D

Semiconductor devices packaging

 

Detail

Committee
Working Groups
Project Leader

Current

Status

Frcst Pub

Date

Stability

Date

SC 47D01I. AnjohMERGED 2014

History

Stage
Document
Downloads
Decision Date
Target Date
PNW
47D/334/NP pdf file 34 kB
1999-12-10 
ANW
47D/366/RVN pdf file 24 kB
2000-04-142000-04-30
ACDV
2000-05-122000-06-30
CCDV
47D/411/CDV pdf file 31 kB
47D/411A/CDV pdf file 12 kB
2001-01-122000-09-30
CDVM
47D/445/RVC pdf file 35 kB
2001-07-062001-09-15
ADIS
2001-10-152001-11-30
DEC
2001-11-132002-02-28
RDIS
2001-11-142002-03-14
CDIS
47D/481/FDIS
2001-12-212002-01-31
APUB
47D/492/RVD pdf file 95 kB
2002-02-252002-04-30
BPUB
2002-02-262002-05-31
MERGED
2002-02-27 
PPUB
 2002-04-30

Project

IEC 60191-2 f46 Ed. 1.0

Small Outline J-Lead Package (SOJ), 0.80 mm Pitch (Outline 163E)

 

Remark:

- EIAJ ED-7406A. - 47D Sec. ref: 98108 - Former F46 has been merged into 60191-2/F40 to become 60191-2/A6 - to be published as Outline 163E

 

Associated Documents:

47D/381/RM

47D/409/RM