International
Electrotechnical
Commission
International Standards and Conformity Assessment
for all electrical, electronic and related technologies
SC 47D |
Semiconductor devices packaging |
Detail
Committee | Working Groups | Project Leader | Current Status | Frcst Pub Date | Stability Date |
|---|---|---|---|---|---|
| SC 47D | 01 | MERGED | 2013 |
History
Stage | Document | Downloads | Decision Date | Target Date | ||
|---|---|---|---|---|---|---|
| PNW |
| 1995-09-22 | ||||
| ANW |
| 1996-02-06 | 1996-02-06 | |||
| 1CD |
| 1996-04-05 | 1998-02-05 | |||
| ACDV |
| 1996-10-04 | 1996-08-31 | |||
| CCDV |
| 1997-06-27 | 1997-05-31 | |||
| ADIS |
| 1999-02-05 | 1998-02-28 | |||
| RDIS | 1999-03-12 | 1999-06-30 | ||||
| CDIS |
| 1999-03-19 | 1999-09-30 | |||
| APUB |
| 1999-07-07 | 1999-06-30 | |||
| BPUB | 1999-07-08 | |||||
| MERGED | 1999-08-17 | |||||
22 kBProject
IEC 60191-2 f24 Ed. 1.0
Plastic small outline family, J-Lead (P-SOJ), 10,16 mm body family (to be published as outline 141E-d)
Remark:
Associated Documents:
47D/149/RM