DEL 191-6 am1 f1 Ed. 1.0

Supplement to IEC 191-6 - Recommended values for dual-in-line packages of Form E

DEL 191-6 am1 f2 Ed. 1.0

Supplement to IEC 191-6 - Recommended values for QFPs of form E

PNW 47D-213 Ed. 1.0

The individual standard for 48 pins plastic fine pitch ball grid array (P-FBGA), 0,75 & 0,65 mm terminal pitch (Intended for inclusion into IEC 191-2)

PNW 47D-252 Ed. 1.0

BGA (Ball Grid Array) package measuring method

PNW 47D-503 Ed. 1.0

Proposed new package outline, 3/4-land SMD

PNW 47D-539 Ed. 1.0

Proposed new package outline, DDRII SDRAM Family, 1,00 mm contact pitch

PNW 47D-540 Ed. 1.0

Proposed new package outline, Plastic, small outline family, 1,27 mm pitch, 7,5 mm body width and 14, 16, 18, 20, 24 and 28 lead counts

PNW 47D-542 Ed. 1.0

Proposed new package outline, Plastic small outline family, 1,27 mm pitch, 3,9 mm body width, 8, 14 and 16 leads

PNW 47D-543 Ed. 1.0

Proposed new package outline, Plastic small outline family, 25 mil pitch, 150 mil body width, 14, 16, 18, 20, 24 and 28 leads

PNW 47D-652 Ed. 1.0

Design guide for semiconductor packages - Ball Grid Array Package (BGA)

PNW 47D-674 Ed. 1.0

Proposed new package outline - 13 Pin reduced size MultiMediaCard (MMC) outline MMCmobile 18 x 24 x 1,4 mm

PNW 47D-675 Ed. 1.0

Proposed new package outline - 10 pin micro size Multimedia Card (MMC) outline MMCmicro 14 x 12 x 1,1 mm (Intended to become IEC 60191-2/F66, if approved)

PNW 47D-676 Ed. 1.0

Proposed new package outline - 13 Pin full size Multimedia Card (MMC) Outline MMCplus 32 x 24 x 1,4 mm (Intended to become IEC 60191-2/F67, if approved)

DEL 60191-1 Ed. 2.0

Systematic review of IEC 191-1 (1966)

IEC 60191-1 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 1: Preparation of drawings of semiconductor devices

IEC 60191-1 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices

IEC 60191-1 fF Ed. 2.0

Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices

IEC 60191-2 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 2: Dimensions

IEC 60191-2 Ed. 2.0

Restructuring of package outlines presently contained in IEC 191-2

IEC 60191-2 f1 Ed. 1.0

Power semiconductor outline Form B, Types A and B, for inclusion into IEC 191-2

IEC 60191-2 f10 Ed. 1.0

Mechanical standardization power devices. Proposal for tablet case outline drawings for two families to be introduced in IEC 191-2 for future use

IEC 60191-2 f11 Ed. 1.0

Ceramic quadrature flat packages, square type, for surface mounting - Introduction of the outline families 130E and 131E in IEC 191-2

IEC 60191-2 f16 Ed. 1.0

Recommended values for QFP, 0.30, 0.40, 0.50, 0.65, 0.80 and 1.00 mm lead spacing, for inclusion into IEC 191-2

IEC 60191-2 f17 Ed. 1.0

Inclusion of a heat sink small outline (HSOP) family, similar to SOP family 075E contained in IEC 191-2

IEC 60191-2 f2 Ed. 1.0

Inclusion of an additional drawing of integrated circuit in the family drawing A50 of IEC 191-2

IEC 60191-2 f2 Ed. 2.0

Tape ball grid array package, 0,6 mm ball diameter family (intended for inclusion into IEC 60191-2)

IEC 60191-2 f24 Ed. 1.0

Plastic small outline family, J-Lead (P-SOJ), 10,16 mm body family (to be published as outline 141E-d)

IEC 60191-2 f25 Ed. 1.0

Plastic thin small outline package P-TSOP II, 7,62 mm body family

IEC 60191-2 f26 Ed. 1.0

P-TSOP II, 10,16 mm body family (if approved, to be included in outline 139 E)

IEC 60191-2 f28 Ed. 1.0

HSOP reverse bend, heatslug up

IEC 60191-2 f29 Ed. 1.0

Plastic thin small outline package J-Lead (P-TSOJ), 7,62 mm body family - (Supplement to IEC 191-2)

IEC 60191-2 f3 Ed. 1.0

General rules for HSOP (Heat sink small outline package) - Supplement to IEC 191-2

IEC 60191-2 f3 Ed. 2.0

48 pins P-FBGA (Plastic Fine pitch Ball Grid Array), 0.75 and 0.65 mm pitch , face down (intended for inclusion into IEC 191-2)

IEC 60191-2 f31 Ed. 1.0

Proposal for a tape ball grid array, 0.75 mm ball diameter family (intended for inclusion into IEC 60191-2) as outline 146E

IEC 60191-2 f33 Ed. 1.0

Ceramic thin LGA, 1,0 mm pitch outline family

IEC 60191-2 f35 Ed. 1.0

4-leaded SMD (Body size DxE:2.00x1.25 mm) (for inclusion into IEC 191-2)

IEC 60191-2 f36 Ed. 1.0

Surface Vertical Packages (SVP) - Outline family 155E

IEC 60191-2 f37 Ed. 1.0

P-VSON (Plastic very small outline - Non-leaded packages) (will be published as Outline 164E-a)

IEC 60191-2 f39 Ed. 1.0

Proposal for 0,8 mm pitch P-FBGA (plastic fine pitch ball grid array)

IEC 60191-2 f4 Ed. 1.0

Tape ball grid array (TBGA) family (Intended for inclusion into 60191-2)

IEC 60191-2 f4 Ed. 2.0

32 and 48 pins P-FBGA (Plastic Fine pitch Ball Grid Array), 0,8 mm pitch (Intended for inclusion into IEC 191-2)

IEC 60191-2 f42 Ed. 1.0

Proposal for a supplement of the rectangular type of QFN outline drawings to the outline family of 119E

IEC 60191-2 f43 Ed. 1.0

Ceramic thin LGA, 0,8 mm pitch outline family

IEC 60191-2 f44 Ed. 1.0

New package outline - Thin fine pitch ball grid array family (rectangular/square)

IEC 60191-2 f46 Ed. 1.0

Small Outline J-Lead Package (SOJ), 0.80 mm Pitch (Outline 163E)

IEC 60191-2 f47 Ed. 1.0

Proposal for 3-Leaded SMD (Body Size D x E : 2.9 x 1.5 mm) Outline Family 162E

IEC 60191-2 f5 Ed. 1.0

Drawing family of rectangular plastic leaded chip carrier (PLCCs) packages - Introduction of the outline family 124E in IEC 191-2

IEC 60191-2 f50 Ed. 1.0

Plastic enhanced, low profile quad flat pack (HLQFP) outline family, heat slug down, L-PQFP-G (Outline 151E-a)

IEC 60191-2 f51 Ed. 1.0

Plastic enhanced, thin profile quad flat pack (HTQFP) outline family, heat slug up, T-PQFP-G (Outline 152E)

IEC 60191-2 f52 Ed. 1.0

Plastic enhanced, thin profile quad flat pack (HTQFP) outline family, heat slug down, T-PQFP-G (Outline 153E)

IEC 60191-2 f55 Ed. 1.0

Small Power Package with 17 Pins (published as Outline 168E)

IEC 60191-2 f58 Ed. 1.0

Proposed new package outline for P-DHVQFN family. (Plastic Dual in-line compatible Heatsink Very thin Quad Flat Pack No Leads)

IEC 60191-2 f62 Ed. 1.0

Amendment 17 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 f64 Ed. 1.0

Proposed new package outline - Small outline package (SOT) 3-, 5- and 6-Lead SMD (to be published as 182E outline)

IEC 60191-2 f67 Ed. 1.0

Proposed new package outline - large power package with 6 load terminals, P-UMP-A6. To be published as outline 185B, if approved.

IEC 60191-2 f68 Ed. 1.0

Proposed new package outline - flange mounted package with through hole leads, P-SFM-T3 - To be published as outline 186F. if approved.

IEC 60191-2 f69 Ed. 1.0

Proposed new package outline - flange mount package with flat leads, P-SFM-F8 - To be published as outline 187E, if approved.

IEC 60191-2 am1 Ed. 1.0

Amendment 1

IEC 60191-2 am1 f1 Ed. 1.0

Inclusion of three drawings for power modules - Supplement to IEC 191-2

IEC 60191-2 am1 f10 Ed. 1.0

Dual in line packages for 0.07 inches pitch (1.778 mm) - Introduction of the outline family 101G in IEC 191-2

IEC 60191-2 am1 f12 Ed. 1.0

Amendment to IEC 191-2 - Single-ended package outline of Form A

IEC 60191-2 am1 f3 Ed. 1.0

Additional outline drawing of power semiconductor device, to be included in IEC 191-2

IEC 60191-2 am1 f4 Ed. 1.0

Integrated circuits - Drawing family of leaded packages of Form E (Quad Flat packages), to be included in IEC 191-2

IEC 60191-2 am1 f5 Ed. 1.0

Amendment to Document 47(C.O.)1148: Inclusion of the outline drawings 121E and 122E in IEC 191-2

IEC 60191-2 am1 f8 Ed. 1.0

Surface mounted cylindrical diodes - Introduction of the outline family 100H in IEC 191-2

IEC 60191-2 am1 f9 Ed. 1.0

Surface mounted packages - Introduction of the outline family 129E in IEC 191-2

IEC 60191-2 am2 Ed. 1.0

Amendment 2

IEC 60191-2 am2 f14 Ed. 1.0

Standard outlines for non-cylindrical surface-mount semiconductors, to be added to IEC 191-2

IEC 60191-2 am2 f15 Ed. 1.0

Inclusion in IEC 191-2 of a wire-ended diode package (small signal diode)

IEC 60191-2 am2 f18 Ed. 1.0

Flange-mounted header family (peripheral terminals) - 0.100 spacing for inclusion in IEC 191-2

IEC 60191-2 am3 Ed. 1.0

Amendment 3

IEC 60191-2 am4 Ed. 1.0

Amendment 4

IEC 60191-2 am5 Ed. 1.0

Amendment 5

IEC 60191-2 am6 Ed. 1.0

Amendment 6

IEC 60191-2 am7 Ed. 1.0

Amendment 7

IEC 60191-2 am8 Ed. 1.0

Amendment 8 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am9 Ed. 1.0

Amendment 9 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am9 f1 Ed. 1.0

Amendment 9

IEC 60191-2 am10 Ed. 1.0

Amendment 10 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am11 Ed. 1.0

Amendment 11 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am12 Ed. 1.0

Amendment 12 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am13 Ed. 1.0

Amendment 13 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am14 Ed. 1.0

Amendment 14 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am15 Ed. 1.0

Amendment 15 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am16 Ed. 1.0

Amendment 16 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am17 Ed. 1.0

Amendment 17 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am18 Ed. 1.0

Amendment 18 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2 am19 Ed. 1.0

Amendment 19 - Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-3 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 3: General rules for the preparation of outline drawings of integrated circuits

IEC 60191-3 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits

IEC 60191-3 f1 Ed. 2.0

Mold flash, interlead flash, gate burrs, and protrusion for plastic packages

IEC 60191-3 f2 Ed. 2.0

Definition of mold flash, interlead flash, gate burrs and protrusions for plastic packages, to be introduced into IEC 191-2

IEC 60191-3 f3 Ed. 2.0

Standardization of Pin #1 mark for identification in automatic handling systems

IEC 60191-3 f4 Ed. 2.0

Definition of pin No. 1 orientation for TAB packages (intended for inclusion into IEC 191-3)

IEC 60191-3 am1 Ed. 1.0

Amendment No. 1

IEC 60191-3 am2 Ed. 1.0

Amendment No. 2

IEC 60191-3 am2 f1 Ed. 1.0

Amendment to Sub-clause 4.5 of IEC 191-3 - Devices with terminals disposed in three or more rows in each orthogonal direction

IEC 60191-4 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 4: Coding systems and classification into forms of package outlines for semiconductor devices

IEC 60191-4 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages

IEC 60191-4 Ed. 2.2

Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages

IEC 60191-4 Ed. 3.0

Mechanical Standardization Of Semiconductor Devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages

IEC 60191-4 f1 Ed. 2.0

Proposed replacement of IEC 191-4: Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor devices

IEC 60191-4 f2 Ed. 2.0

Amendment to IEC 191-4 to add a package style and a descriptive designator for high power semiconductor packages (100 ... 1700 V/10 ... 1000 A)

IEC 60191-4 f3 Ed. 2.0

Definition and value of L, T

IEC 60191-4 am1 Ed. 2.0

Amendment 1

IEC 60191-4 am2 Ed. 2.0

Amendment 2

IEC 60191-5 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 5: Recommendations applying to tape automated bonding (TAB) of integrated circuits

IEC 60191-5 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 5: Recommendations applying to integrated circuit packages using tape automated bonding (TAB)

IEC 60191-6 Ed. 1.0

Mechanical standardization of semiconductor devices. Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

IEC 60191-6 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

IEC 60191-6 Ed. 3.0

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

DEL 60191-6 am1 f1 Ed. 1.0

Inclusion of an SVP outline family into IEC 191-6

DEL 60191-6 am1 f3 Ed. 1.0

O value of leaded packages with two parallel rows of terminals in IEC 191-6, Appendix B1

IEC 60191-6 am1 Ed. 1.0

Amendment 1

IEC 60191-6 am1 f5 Ed. 1.0

IEC 191-6 - General rules for TSOP (Thin small outline package) Type II

IEC 60191-6 am2 f8 Ed. 1.0

Amendment to IEC 60191-6 - Renaming 'terminal land area' to 'terminal position area'

IEC 60191-6-1 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-1: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for gull-wing lead terminals

IEC 60191-6-1 Ed. 2.0

IEC 60191-6-1 Ed.2: Part 6-1: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for gull-wing lead terminals

IEC 60191-6-2 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages

IEC 60191-6-2 fC1 Ed. 1.0

Corrigendum 1

IEC 60191-6-2 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-2: General rules for the preparation of outline drawings of surface mounted semiconductor devices packages - Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column terminal packages

IEC 60191-6-3 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-3: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of quad flat packs (QFP)

IEC 60191-6-3 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-3: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of quad flat packs (QFP)

IEC 60191-6-4 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)

IEC 60191-6-4 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-4: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of ball grid array (BGA)

IEC 60191-6-5 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

IEC 60191-6-5 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

IEC 60191-6-6 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA)

IEC 60191-6-6 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA)

IEC 60191-6-7 Ed. 1.0

Mechanical standardization of semiconductor devices - part 6-7: General rules for the dimensions of P-VQFN

IEC 60191-6-8 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-8: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for glass sealed ceramic quad flatpack (G-QFP)

IEC 60191-6-8 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-8: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for glass sealed ceramic quad flatpack (G-QFP)

IEC 60191-6-9 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-9: General rules for the preparation of outline drawing of surface mounted semiconductor device packages - Design guideline of integrated circuits for Plastic Quad Flat Package (P-QFP)

IEC 60191-6-10 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON

IEC 60191-6-10 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-10: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Dimensions of P-VSON

IEC 60191-6-11 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-11: General design guidelines for rectangular Fine Pitch Ball Grid Array Packages (FBGA)

IEC 60191-6-12 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch land grid array (FLGA) - Rectangular type

IEC 60191-6-12 Ed. 2.0

Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA)

IEC 60191-6-13 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-13: Design guideline of open-top-type sockets for Fine-pitch Ball Grid Array and Fine-pitch Land Grid Array (FBGA/FLGA)

IEC 60191-6-13 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-13: Design guideline of open-top-type sockets for Fine-pitch Ball Grid Array and Fine-pitch Land Grid Array (FBGA/FLGA)

IEC 60191-6-14 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-14: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)

IEC 60191-6-15 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-15: General rules for the preparation of outline drawings of surface mounted semiconductor device packages- Measuring methods for package dimensions of small outline packages (SOP)

IEC 60191-6-16 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA

IEC 60191-6-16 fF Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA

IEC 60191-6-17 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

IEC 60191-6-18 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)

IEC 60191-6-18 fC1 Ed. 1.0

Corrigendum 1 - Mechanical stardardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)

IEC 60191-6-18 fC2 Ed. 1.0

Corrigendum 2 - Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)

IEC/PAS 60191-6-18 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-18: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for ball grid array (BGA)

IEC 60191-6-19 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of the package warpage at elevated temperature and the maximum permissible warpage

IEC/PAS 60191-6-19 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-19: Measurement methods of package warpage at elevated temperature and the maximum permissible warpage

IEC 60191-6-20 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ)

IEC 60191-6-21 Ed. 1.0

MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - Part 6-21: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline packages (SOP)

IEC 60191-6-22 Ed. 1.0

Mechanical standardization of semiconductor devices - Part 6-22: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for semiconductor packages Silicon Fine-pitch Ball Grid Array and Silicon Fine-pitch Land Grid Array (S-FBGA and S-FLGA)

IEC 60191-1A Ed. 1.0

Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - First supplement

IEC 60191-1B Ed. 1.0

Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - Second supplement

IEC 60191-1C Ed. 1.0

Mechanical standardization of semiconductor devices - Part 1: Preparation of drawings of semiconductor devices - Third supplement

IEC 60191-2A Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - First supplement

IEC 60191-2B Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Second supplement

IEC 60191-2C Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Third supplement

IEC 60191-2D Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Fourth supplement

IEC 60191-2E Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Fifth supplement

IEC 60191-2F Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Sixth supplement

IEC 60191-2G Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Seventh supplement

IEC 60191-2H Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Eighth supplement

IEC 60191-2J Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Ninth supplement

IEC 60191-2K Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Tenth supplement

IEC 60191-2L Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Eleventh supplement

IEC 60191-2M Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Twelfth supplement

IEC 60191-2N Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Thirteenth supplement

IEC 60191-2P Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Fourteenth supplement

IEC 60191-2Q Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions - Fifteenth supplement

IEC 60191-2R Ed. 1.0

Sixteenth supplement

IEC 60191-2S Ed. 1.0

Seventeenth supplement

IEC 60191-2T Ed. 1.0

Eighteenth supplement to IEC 191-2

IEC 60191-2U Ed. 1.0

Nineteenth supplement

IEC 60191-2V Ed. 1.0

Twentieth supplement

MERGED 60191-2V Ed. 1.0

Twentieth supplement to IEC 191-2

IEC 60191-2W Ed. 1.0

Twenty-first supplement

IEC 60191-2W f1 Ed. 1.0

Proposal for a plastic thin shrink small outline package (TSSOP/HTSSOP), 1,00 mm lead length outline family, R-PDSO-G

DEL 60191-2X Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2X: Dimensions - 102F outline family

IEC 60191-2X Ed. 1.0

Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-2X fC1 Ed. 1.0

Corrigendum 1

IEC 60191-2Y Ed. 1.0

Vingt-troisième complément à la Publication 60191-2 (1966)

IEC 60191-2Y f30 Ed. 1.0

Addition to the metric plastic quad flatpack family; 1.0 mm, 0,80 mm and 0,65 mm

IEC 60191-2Z Ed. 1.0

Twenty-fourth supplement to Publication 60191-2 (1966) Mechanical standardization of semiconductor devices - Part 2: Dimensions

IEC 60191-3A Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - First supplement

IEC 60191-3B Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Second supplement

IEC 60191-3C Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Third supplement

IEC 60191-3D Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Fourth supplement

IEC 60191-3E Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Fifth supplement

IEC 60191-3F Ed. 1.0

Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits - Sixth supplement

IEC 61927 Ed. 1.0

Dimensional check of surface mounted devices